Adaptive voltage scaling may be used on system-on-a-chip (SOC) designs to save dynamic power and leakage power. Process, power supply voltage level, and temperature (PVT) corners may cause variation in timing for paths of an integrated circuit (IC) chip. For example, the delay for a NAND gate in a worst case scenario (e.g., slowest PVT corner) may be several times more than that in a best case scenario (e.g., fastest PVT corner).
Adaptive voltage scaling may be used to improve the power consumption on the IC. Adaptive voltage scaling may be used to apply a minimum power supply voltage that is required to meet critical path timing in a PVT corner for the chip. For example, if the critical path timing delay is determined as being unnecessarily fast, the power supply voltage may be lowered to increase the critical path timing delay. Lowering the power supply voltage increases the delay to bring the real critical path timing closer to the desired timing budget or margin. Also, by lowering the voltage, power may be saved. In another example, if the real critical path delay is determined as being greater than the desired timing budget, then the power supply voltage can be increased to decrease the critical path delay to bring the delay closer to the desired timing budget.